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US 2021/0173312 A1Published application
Lithography supports with defined burltop topography
AssigneeASML Holding N.V.
InventorsMatthew LIPSON, David Allen HEALD, Iliya SIGAL
Life of this patent
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Abstract
Methods and systems are described for reducing adhesion and controlling friction between a wafer and a wafer table during semiconductor photolithography wherein the tops of burls on the wafer table have a layer with a nanoscale topography.
Claims28
A wafer table comprising:
- a wafer table body;
- a plurality of burls formed on the wafer table body, each of the burls comprising a burl body, and
- a layer formed on top of the burl body, a top of the layer having a plurality of nanoscale structures.
A wafer table comprising a plurality of burls, each of the burls comprising a burl body and a layer comprising a ceramic material formed on top of the burl body, a top of the layer having a nanoscale topography.
A method comprising the steps of:
- providing a wafer table comprising a plurality of burls;
- and
- forming a layer on top of the burls.
Dependencies are inferred from the claim text.