Address interleaving for machine learning
AssigneeMarvell Asia Pte Ltd
InventorsAvinash Sodani, Ramacharan Sundararaman
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Abstract
A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.
Claims19
A system to support a machine learning (ML) operation, comprising:
- a memory configured to store data;
- an array-based inference engine comprising a plurality of processing tiles arranged in a two-dimensional array of a plurality of rows and a plurality of columns, wherein each processing tile comprises at least one or more of
- an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile;
- and
- one or more processing units configured to perform one or more computation tasks of the ML operation on data in the OCM by executing a set of task instructions;
- and
- a data streaming engine configured to stream data between the memory and the OCMs of the processing tiles of the inference engine, wherein the data streaming engine is configured to interleave an address associated with a memory access transaction for accessing the memory;
- and
- a network interface controller configured to support address interleaving for a burst length greater than a burst length of the address.
A system comprising:
- a memory configured to store data;
- an inference engine configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data;
- a master configured to interleave an address associated with a memory access transaction for accessing the memory, and wherein the master is further configured to stream a content associated with the accessing to the inference engine;
- and
- a network interface controller configured to support address interleaving for a burst length greater than a burst length of the address.
A method to support a machine learning (ML) operation, comprising:
- interleaving an address associated with a memory access transaction for accessing a memory, wherein interleaving of the address is for a burst length greater than a burst length of the address;
- streaming data associated with the memory accessing transaction from the memory to an inference engine;
- and
- performing one or more computation tasks of the ML operation associated with the data via the inference engine.
Dependencies are inferred from the claim text.