Semiconductor integrated circuit, a/d converter, delta sigma-type a/d converter, incremental delta sigma-type a/d converter, and switched capacitor

A semiconductor integrated circuit, comprising:

• a sample and hold circuit having a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage;
• and
• a clock generation circuit that generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal,
• wherein the clock generation circuit comprises:
• a delay adjustment circuit that performs adjustment to delay the second clock signal to bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal, and
• a level-up circuit that shifts a voltage level of the first clock signal to a voltage level related to the second withstand voltage,
• the delay adjustment circuit coupled to at least one of a front stage of the level-up circuit and a subsequent stage of the level-up circuit.