Inner spacers for gate-all-around semiconductor devices

A method of fabricating a semiconductor device, comprising:

• providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
• forming a dummy gate structure over a channel region of the fin element;
• etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers;
• selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
• depositing an inner spacer layer over the plurality of recesses using an organosilane precursor and a nitrogen-containing gas;
• treating the inner spacer layer;
• and
• etching back the inner spacer layer.

A method of fabricating a semiconductor device, comprising:

• providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
• forming a dummy gate structure over a channel region of the fin element;
• etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers,
• selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
• depositing an inner spacer layer comprising silicon and nitrogen;
• treating the inner spacer layer;
• and
• etching back the inner spacer layer to form a porous silicon nitride layer that is less dense than silicon nitride.