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US 2021/0083084 A1Published application
Semiconductor device and fabricating method thereof
AssigneeUnited Microelectronics Corp.
InventorsChun-Ming Chang, Wen-Jung Liao
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Abstract
A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.
Claims20
1:
- A semiconductor device, comprising:
- an enhancement mode high electron mobility transistor (HEMT) comprising an active region and an isolation region, wherein the enhancement mode HEMT comprises:
- a substrate;
- a group III-V body layer, disposed on the substrate;
- a group III-V barrier layer, disposed on the group III-V body layer in the active region and the isolation region, wherein the group III-V barrier layer comprises a first thickness and a second thickness which are different from each other in the active region;
- and
- a recess, disposed in the group III-V barrier layer in the active region.
4 more elements
2:
- The semiconductor device of claim 1, wherein the group III-V barrier layer in the active region has the first thickness between 2 and 10 nm.
3:
- The semiconductor device of claim 1, further comprising a gate electrode disposed in the recess and electrically coupled to the group III-V barrier layer in the active region.
4:
- The semiconductor device of claim 1, wherein the semiconductor device further comprises at least two source/drain electrodes disposed in the active region.
5:
- The semiconductor device of claim 1, further comprising an etch mask layer disposed on a top surface of the group III-V barrier layer and spaced apart from the recess.
6:
- The semiconductor device of claim 5, wherein a composition of the etch mask layer comprises silicon nitride or silicon oxide.
7:
- The semiconductor device of claim 1, wherein the semiconductor device further comprises another recess disposed in the group III-V barrier layer of the isolation region.
8:
- The semiconductor device of claim 7, wherein the group III-V barrier layer in the isolation region has a thickness between 2 and 10 nm.
9:
- The semiconductor device of claim 7, wherein the semiconductor device further comprises a passivation layer disposed in the recesses of the active region and the isolation region.
10:
- The semiconductor device of claim 9, further comprising an etch mask layer disposed between the passivation layer and the group III-V barrier layer in the active region, wherein the etch mask layer is spaced apart from bottoms of the recesses in the active region and the isolation region.
11:
- The semiconductor device of claim 9, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.
12:
- The semiconductor device of claim 1, further comprising another enhancement mode high electron mobility transistor disposed on a side of the enhancement mode HEMT, wherein the group III-V barrier layer is a continuous layer disposed between the enhancement mode HEMTs.
13:
- A method of fabricating a semiconductor device comprising an active region and an isolation region, the method comprising:
- providing a substrate having a group III-V body layer and a group III-V barrier layer thereon;
- forming a first recess and a second recess in the group III-V barrier layer, wherein the first recess and the second recess are in the active region and the isolation region respectively;
- and
- depositing a passivation layer at bottoms of the first recess and the second recess, wherein portions of the group III-V barrier layer is disposed under the first recess and the second recess.
2 more elements
14:
- The method of fabricating the semiconductor device of claim 13, wherein the first recess and the second recess are formed concurrently.
15:
- The method of fabricating the semiconductor device of claim 13, wherein the group III-V barrier layer in the active region has a thickness between 2 and 10 nm.
16:
- The method of fabricating the semiconductor device of claim 13, wherein a composition of the passivation layer comprises aluminum nitride, aluminum oxide or silicon nitride.
17:
- The method of fabricating the semiconductor device of claim 13, further comprising:
- forming a patterned etch mask layer on the group III-V barrier layer;
- and
- etching the group III-V barrier layer by using the patterned etch mask as an etch mask.
1 more element
18:
- The method of fabricating the semiconductor device of claim 17, wherein a composition of the etch mask layer comprises silicon nitride or silicon oxide.
19:
- The method of fabricating a semiconductor device of claim 17, wherein the etch mask layer is disposed between the passivation layer and the group III-V barrier layer in the active region.
20:
- The method of fabricating a semiconductor device of claim 17, further comprising forming a gate electrode and at least two source/drain electrodes respectively penetrating the passivation layer, wherein the electrodes are spaced apart from the group III-V barrier layer at the bottom of the second recess.