Field effect transistor with negative capacitance dieletric structures

A method of fabricating a semiconductor device, the method comprising:

• forming a fin structure with a stacked fin portion and a fin base portion on a substrate, wherein the stacked fin portion is epitaxially grown on the fin base portion;
• forming an epitaxial source/drain region on the fin structure;
• forming a first negative capacitance (NC) dielectric structure in a first region of the stacked fin portion, wherein the first NC dielectric structure comprises a first dielectric layer with a first NC material;
• forming gate structures on a second region of the stacked fin portion, wherein the gate structures each comprises a second dielectric layer with the first NC material;
• forming a source/drain contact structure on the epitaxial source/drain region;
• and
• forming a second NC dielectric structure between the source/drain contact structure and the gate structures, wherein the second NC dielectric structure comprises a third dielectric layer with the first NC material.

A method of fabricating a semiconductor device, the method comprising:

• forming a fin structure with a fin base portion and a fin top portion on a substrate;
• forming a spacer structure in a first region of the fin top portion, wherein the spacer structure comprises a negative capacitance (NC) dielectric layer comprising an NC dielectric material, a non-NC dielectric structure, and an air gap;
• forming a source/drain region on the fin base portion and in contact with the fin top portion, wherein the source/drain region, the NC dielectric layer, and the non-NC dielectric structure encloses the air gap;
• and
• forming a gate structure on a second region of the fin top portion, wherein the gate structure comprises a gate dielectric layer having the NC dielectric material.