Transistor comprising a matrix of nanowires and methods of making such a transistor

A transistor device, comprising:

• a nanowire matrix comprising a plurality of nanowire structures that are arranged in a plurality of horizontally oriented rows and a plurality of substantially vertically oriented columns, the plurality of substantially horizontally oriented rows being vertically spaced apart from one another, the plurality of substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter;
• a gate structure, the gate structure being positioned around the outer perimeter of all of the nanowire structures in the matrix;
• a gate cap positioned above the gate structure;
• a first region of epitaxial semiconductor material positioned in a source region of the transistor device that conductively contacts the plurality of nanowire structures in the nanowire matrix;
• and
• a second region of epitaxial semiconductor material positioned in a drain region of the transistor device that conductively contacts the plurality of nanowire structures in the nanowire matrix.

A transistor device, comprising:

• a nanowire matrix comprising a plurality of nanowire structures that are arranged in a plurality of horizontally oriented rows and a plurality of substantially vertically oriented columns, the plurality of substantially horizontally oriented rows being vertically spaced apart from one another, the plurality of substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter;
• an insulating material positioned between and engaging the nanowire structures in each of the plurality of horizontally oriented rows of nanowire structures;
• a gate structure, the gate structure being positioned around the outer perimeter of all of the nanowire structures in the matrix;
• a gate cap positioned above the gate structure;
• a first region of epitaxial semiconductor material positioned in a source region of the transistor device that conductively contacts the plurality of nanowire structures in the nanowire matrix;
• and
• a second region of epitaxial semiconductor material positioned in a drain region of the transistor device that conductively contacts the plurality of nanowire structures in the nanowire matrix.