Memory cell arrangement and methods thereof

Memory cell arrangement, comprising:

• a first electrode layer comprising at least a first through hole, a second through hole, a third through hole, and a fourth through hole, each of the first through hole, the second through hole, the third through hole, and the fourth through hole extending from a first surface of the first electrode layer to a second surface of the first electrode layer, wherein the second surface is opposite the first surface;
• a second electrode layer comprising at least a first through hole, a second through hole, a third through hole, and a fourth through hole, each of the first through hole, the second through hole, the third through hole, and the fourth through hole extending from a first surface of the second electrode layer to a second surface of the second electrode layer, wherein the second surface is opposite the first surface;
• a first electrode pillar, wherein a first portion of the first electrode pillar is disposed within the first through hole of the first electrode layer and wherein a second portion of the first electrode pillar is disposed within the first through hole of the second electrode layer;
• a second electrode pillar, wherein a first portion of the second electrode pillar is disposed within the second through hole of the first electrode layer and wherein a second portion of the second electrode pillar is disposed within the second through hole of the second electrode layer;
• a third electrode pillar, wherein a first portion of the third electrode pillar is disposed within the third through hole of the first electrode layer and wherein a second portion of the third electrode pillar is disposed within the third through hole of the second electrode layer;
• a fourth electrode pillar, wherein a first portion of the fourth electrode pillar is disposed within the fourth through hole of the first electrode layer and wherein a second portion of the fourth electrode pillar is disposed within the fourth through hole of the second electrode layer;
• a first remanent-polarizable portion disposed at least within the first through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the first electrode pillar that is disposed within the first through hole of the first electrode layer;
• a second remanent-polarizable portion disposed at least within the first through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the first electrode pillar that is disposed within the first through hole of the second electrode layer;
• a third remanent-polarizable portion disposed at least within the second through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the second electrode pillar that is disposed within the second through hole of the first electrode layer;
• and
• a fourth remanent-polarizable portion disposed at least within the second through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the second electrode pillar that is disposed within the second through hole of the second electrode layer;
• a fifth remanent-polarizable portion disposed at least within the third through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the third electrode pillar that is disposed within the third through hole of the first electrode layer;
• a sixth remanent-polarizable portion disposed at least within the third through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the third electrode pillar that is disposed within the third through hole of the second electrode layer;
• a seventh remanent-polarizable portion disposed at least within the fourth through hole of the first electrode layer in a gap between the first electrode layer and the first portion of the fourth electrode pillar that is disposed within the fourth through hole of the first electrode layer;
• an eighth remanent-polarizable portion disposed at least within the fourth through hole of the second electrode layer in a gap between the second electrode layer and the second portion of the fourth electrode pillar that is disposed within the fourth through hole of the second electrode layer;
• wherein the first electrode layer, the first portion of the first electrode pillar, and the first remanent-polarizable portion form a first memory cell;
• wherein the second electrode layer, the second portion of the first electrode pillar, and the second remanent-polarizable portion form a second memory cell;
• wherein the first electrode layer, the first portion of the second electrode pillar, and the third remanent-polarizable portion form a third memory cell;
• wherein the second electrode layer, the second portion of the second electrode pillar, and the fourth remanent-polarizable portion form a fourth memory cell;
• wherein the first electrode layer, the first portion of the third electrode pillar, and the fifth remanent-polarizable portion form a fifth memory cell;
• wherein the second electrode layer, the second portion of the third electrode pillar, and the sixth remanent-polarizable portion form a sixth memory cell;
• wherein the first electrode layer, the first portion of the fourth electrode pillar, and the seventh remanent-polarizable portion form a seventh memory cell;
• wherein the second electrode layer, the second portion of the fourth electrode pillar, and the eighth remanent-polarizable portion form an eighth memory cell;
• a first access device configured to connect a first bitline to the first electrode pillar controlled by a voltage applied at a first wordline;
• a second access device configured to connect the first bitline to the second electrode pillar controlled by a voltage applied at a second wordline;
• a third access device configured to connect a second bitline to the third electrode pillar controlled by a voltage applied at the first wordline;
• a fourth access device configured to connect the second bitline to the fourth electrode pillar controlled by a voltage applied at the second wordline;
• a control circuit configured to address one of the first memory cell, the second memory cell, the third memory cell, the fourth memory cell, the fifth memory cell, the sixth memory cell, the seventh memory cell, or the eighth memory cell by supplying a first voltage to the associated one of the first bitline or the second bitline, a second voltage to the associated one of the first wordline or the second wordline, and a third voltage to the associated one of the first electrode layer or the second electrode layer.

Method for manufacturing a memory cell arrangement, the method comprising:

• forming an electrode layer stack at least one of over or in a substrate, wherein the electrode layer stack comprises at least a first electrode layer, a second electrode layer, and an electrically isolating interlayer disposed between the first electrode layer and the second electrode layer;
• forming one or more recesses into the electrode layer stack, wherein the one or more recesses extend at least through the first electrode layer, the interlayer, and the second electrode layer,
• partially filling the one or more recesses with a remanent-polarizable material, the remanent-polarizable material at least covering a sidewall of each of the one or more recesses;
• and, subsequently,
• at least partially filling a remaining space in each of the one or more recesses with an electrode material, wherein, in each of the one or more recesses, a portion of the remanent-polarizable material is disposed between a portion of the electrode material and one of the electrode layers.