Semiconductor memory device

A semiconductor memory device comprising:

• an array region;
• and
• an edge region surrounding the array region,
• wherein the array region includes:
• a first interconnect layer;
• a second interconnect layer electrically coupled to the first interconnect layer;
• a plurality of third interconnect layers stacked apart from each other in a first direction between the first interconnect layer and the second interconnect layer in the first direction, and extending in a second direction that intersects the first direction;
• a first insulating layer passing through the plurality of third interconnect layers, including one end that is in contact with a first face of the first interconnect layer, and extending in the second direction;
• a first memory pillar including a first semiconductor layer and a charge storage layer, the first semiconductor layer passing through the plurality of third interconnect layers, including a side face in contact with a second face of the first insulating layer extending in the second direction and facing a third direction intersecting the first and second directions, including one end in contact with the first face of the first interconnect layer, and extending in the first direction, and the charge storage layer being capable of storing data and provided between the plurality of third interconnect layers and the first semiconductor layer, and
• the edge region includes a plurality of second semiconductor layers and a plurality of third semiconductor layers that are stacked alternately.

A semiconductor memory device comprising:

• a first interconnect layer;
• a second interconnect layer electrically coupled to the first interconnect layer;
• a plurality of third interconnect layers stacked between the first interconnect layer and the second interconnect layer in a first direction and extending in a second direction intersecting the first direction;
• a plurality of first insulating layers stacked alternately with the plurality of third interconnect layers in the first direction and extending in the second direction;
• a second insulating layer passing through the plurality of third interconnect layers, including one end that is in contact with a first face of the first interconnect layer, and extending in the second direction;
• a first memory pillar including a first semiconductor layer and a charge storage layer, the first semiconductor layer passing through the plurality of third interconnect layers, including a side face in contact with a second face of the second insulating layer extending in the second direction and facing a third direction intersecting the first and second directions, including one end in contact with the first face of the first interconnect layer, and extending in the first direction, and the charge storage layer being capable of storing data and provided between the plurality of third interconnect layers and the first semiconductor layer,
• wherein a distance between the one end of the second insulating layer and the second interconnect layer is longer than a distance between the first insulating layer located closest to the second interconnect layer and the second interconnect layer in the first direction.