Three-dimensional semiconductor memory device

A semiconductor memory device, comprising:

• a peripheral circuit structure on a substrate;
• a semiconductor layer on the peripheral circuit structure;
• an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer;
• a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer;
• a separation structure penetrating the electrode structure and horizontally dividing at least one of the electrodes of the electrode structure into a pair of electrodes;
• a cell contact plug penetrating a staircase structure of the electrode structure;
• an interlayered insulating layer covering the electrode structure;
• and
• a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure,
• wherein the separation structure includes a lower separation structure and an upper separation structure on the lower separation structure, and
• a width of an upper portion of the lower separation structure is larger than a width of a lower portion of the upper separation structure.

A semiconductor memory device, comprising:

• a peripheral circuit structure on a substrate, the peripheral circuit structure including a peripheral transistor on the substrate, a peripheral interconnection line on the peripheral transistor, and a peripheral contact electrically connecting the peripheral transistor to the peripheral interconnection line;
• a semiconductor layer on the peripheral circuit structure;
• an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer;
• a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer;
• a separation structure penetrating the electrode structure extending in a first direction and horizontally dividing a first electrode of the electrodes into a pair of electrodes;
• a cell contact plug penetrating a staircase structure of the electrode structure and electrically connected to a second electrode of the electrodes;
• an interlayered insulating layer covering the electrode structure;
• a through contact penetrating the interlayered insulating layer and electrically connected to the peripheral interconnection line of the peripheral circuit structure;
• and
• a bit line and a connection line on the interlayered insulating layer,
• wherein the vertical channel structure includes,
• a vertical semiconductor pattern having a shape like a pipe with an open top end, and
• a vertical insulating pattern including a data storing layer, the data storing layer interposed between the vertical semiconductor pattern and a third electrode of the electrodes, wherein
• the bit line is electrically connected to the vertical semiconductor pattern,
• the connection line is electrically connected to the through contact, and
• a top surface of the separation structure, a top surface of the vertical channel structure, a top surface of the cell contact plug, and a top surface of the through contact are coplanar with each other.