Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array
AssigneeKey Foundry Co., Ltd.
InventorsSu Jin KIM, Hye Jin YOO
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Abstract
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
Claims18
An array of non-volatile memory cells, each memory cell comprising:
- a selection transistor comprising a source electrode and a selection gate electrode;
- a sensing transistor comprising a drain electrode and a sensing gate;
- a control gate electrode disposed adjacent to a control gate;
- a source line coupled to the source electrode of the selection transistor for receiving a source voltage;
- a selection gate line coupled to the selection gate electrode of the selection transistor for receiving a selection gate voltage;
- a bit line coupled to the drain electrode of the sensing transistor for receiving a drain voltage;
- a control gate line coupled to the control gate electrode for receiving a control gate voltage;
- and
- a floating gate connected to the control gate and the sensing gate,
- wherein the floating gate is configured to charge or discharge electric charges according to a voltage applied to the control gate electrode and the source electrode.
An array of non-volatile memory cells, the array comprising:
- a first non-volatile memory cell array comprising:
- a first selection transistor comprising a first source electrode and a first selection gate electrode;
- a first sensing transistor comprising a first drain electrode and a first sensing gate;
- a first control gate electrode disposed adjacent to a first control gate;
- and
- a first floating gate connected to the first sensing gate and the first control gate, and
- a second non-volatile memory cell array comprising:
- a second selection transistor comprising a second source electrode and a second selection gate electrode;
- a second sensing transistor comprising a second drain electrode;
- and
- a second control gate electrode disposed adjacent to a second control gate;
- a first source line coupled to the first source electrode of the first selection transistor and the second source electrode of the second selection transistor;
- a first bit line coupled to the first drain electrode of the first sensing transistor and the second drain electrode of the second sensing transistor;
- a first selection gate line coupled to the first selection gate electrode of the first selection transistor;
- and
- a first control gate line coupled to the first control gate electrode.
Dependencies are inferred from the claim text.