Embedded memory with improved fill-in window

An integrated circuit (IC), comprising:

• a substrate including a memory region and a logic region;
• a memory cell structure disposed on the memory region and comprising a select gate electrode;
• a logic device disposed on the logic region and comprising a logic gate electrode separated from the substrate by a logic gate dielectric;
• a sidewall spacer along a sidewall surface of the logic gate electrode;
• a lower inter-layer dielectric layer surrounding the memory cell structure;
• and
• a contact etch stop layer (CESL) disposed along an outline of the memory cell structure and is in direct contact with a sidewall surface of the select gate electrode.

An integrated circuit (IC), comprising:

• a substrate including a memory region and a logic region;
• a memory cell structure disposed on the memory region, wherein the memory cell structure comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;
• a logic device on the logic region and comprising a logic gate electrode and a logic gate dielectric stacked on the logic region;
• a sidewall spacer along a sidewall surface of the logic gate electrode;
• source/drain regions on opposite sides of the pair of select gate electrodes within the memory region and on opposite sides of the sidewall spacer within the logic region;
• and
• a contact etch stop layer (CESL) along sidewalls of the memory cell structure and the logic device.