Semiconductor memory devices

A semiconductor memory device comprising:

• a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein;
• a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each bit line structure including a bit line;
• a plurality of gate line structures in the peripheral region, each of the plurality of gate line structures having a gate line pattern at the same level as the bit line;
• a buried contact filling a lower portion of a space between the plurality of bit line structures on the substrate;
• a landing pad on the buried contact;
• and
• a dam structure arranged along sides of the rectangular shape of the memory cell region in the dam region,
• wherein a side of a top surface of the dam structure extends in a straight line and faces the memory cell region.

A semiconductor memory device comprising:

• a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein;
• a plurality of word lines extending across the plurality of active regions in the memory cell region in a first horizontal direction, the plurality of word lines being parallel with each other;
• a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a second horizontal direction that is perpendicular to the first horizontal direction, each bit line structure including a bit line;
• a plurality of gate line structures in the peripheral region, each of the plurality of gate line structures having a gate line pattern at the same level as the bit line in a vertical direction;
• a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate;
• a plurality of landing pads filling upper portions of the spaces among the plurality of bit line structures and extending over the plurality of bit line structures;
• and
• a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads in the vertical direction,
• wherein the first dam structure has a line shape extending in the first horizontal direction,
• wherein the second dam structure has a line shape extending in the second horizontal direction,
• wherein the first dam structure and the second dam structure are separated from each other by a first dam opening at a corner of the rectangular shape of the memory cell region,
• wherein each of the plurality of landing pads has a top surface having a disc shape,
• wherein opposite sides of a top surface of the first dam structure extend in straight lines in the first horizontal direction,
• wherein opposite sides of a top surface of the second dam structure extend in straight lines in the second horizontal direction, and
• wherein the opposite sides respectively face the memory cell region and the peripheral region.