Semiconductor storage device

A semiconductor storage device, comprising:

• a first plurality of first wires extending in a first direction spaced from each other in a second direction intersecting the first direction;
• a plurality of second wires extending in the second direction and spaced from each other in the first direction, the plurality of second wires being spaced from the first plurality of first wires in a third direction orthogonal to the first and second directions;
• and
• a first plurality of channel layers extending in the third direction, each channel layer of the first plurality facing a first wire of the first plurality and connected to a second wire of the plurality of second wires, each channel layer of the first plurality intersecting the first wire at a position in central portion of the first wire in the second direction and intersecting the second wire at a first outer edge of the second wire, the channel layer of the first plurality being on a surface of the second wire facing the first wire in the third direction and overlapping the first outer edge to be on a side surface of the second wire facing in the first direction.

A semiconductor storage device, comprising:

• a first plurality of word lines extending in a first direction and spaced from each other in a second direction intersecting the first direction, the first plurality of word lines being at a first distance from a substrate in a third direction orthogonal to the first and second direction;
• a plurality of bit lines extending in the second direction and spaced from each other in the first direction, the plurality of bit lines being at a second distance from the substrate in the third direction, the second distance being greater than the first distance;
• a second plurality of word lines extending in the first direction and spaced from each other in the second direction, the second plurality of word lines being at a third distance from the substrate in the third direction, the third distance being greater than the second distance, the plurality of bit lines being between the first and second plurality of word lines in the third direction, word lines of the first and second pluralities being aligned with each other in the third direction;
• a first plurality of channel layers extending in the third direction, a channel layer of the first plurality connected to a bit line of the plurality of bit lines and facing a word line of the first plurality, an upper end of the channel layer of the first plurality contacting a side surface of the bit line and a lower surface of the bit line facing the first plurality of word lines;
• and
• a second plurality of channel layers extending in the third direction, a channel layer of the second plurality connected to a bit line of the plurality of bit lines and facing a word line of the second plurality, a lower end of the channel layer of the second plurality contacting a side surface of the bit line and a upper surface of the bit line facing the second plurality of word lines, wherein
• the channel layer of the first plurality extends through a central portion of the word line of the first plurality,
• the channel layer of the second plurality extends through a central portion of the word line of the second plurality,
• a first capacitor is connected to a lower end of the channel layer of the first plurality in the third direction, and
• a second capacitor connected to an upper end of the channel layer of the second plurality in the direction.

A semiconductor storage device, comprising:

• a plurality of first wires extending in a first direction;
• a plurality of second wires extending in a second direction intersecting the first direction;
• a plurality of first semiconductor transistors, one of the first semiconductor transistors including a gate electrode and a channel layer, the gate electrode connected to one of the first wires and one end of the channel layer connected to a first surface and a second surface of one of the second wires, the first surface facing in a third direction intersecting the first and second directions and the second surface facing in a direction intersecting the third direction;
• and
• a capacitor connected to another end of the channel layer in the third direction.