Semiconductor device

A semiconductor device comprising a transistor, and the transistor comprising:

• a first conductive layer;
• a first insulating layer over the first conductive layer;
• a second insulating layer over the first insulating layer;
• a first oxide over the second insulating layer;
• a second oxide over the first oxide;
• a third oxide over the second oxide;
• a third insulating layer over the third oxide;
• a second conductive layer over the third insulating layer;
• a third conductive layer and a fourth conductive layer over the second oxide;
• a fifth conductive layer over the third conductive layer;
• and
• a sixth conductive layer over the fourth conductive layer,
• wherein the first conductive layer and the second conductive layer overlap with the second oxide,
• wherein the fifth conductive layer is in contact with a side surface of the third conductive layer on a second conductive layer side, and in contact with a top surface of the second oxide,
• wherein the sixth conductive layer is in contact with a side surface of the fourth conductive layer on the second conductive layer side, and in contact with the top surface of the second oxide,
• wherein, in a channel width direction of the transistor, a bottom surface of the second oxide is below a first region of a bottom surface of the second conductive layer,
• wherein the first region of the bottom surface of the second conductive layer does not overlap with the second oxide and the first oxide, and
• wherein, when a level of the first region of the bottom surface of the second conductive layer is regarded as a reference, a level of the bottom surface of the second oxide from the reference is more than or equal to −5 nm to less than 0 nm.

A semiconductor device comprising a transistor, and the transistor comprising:

• a first gate electrode;
• a first insulating layer over the first gate electrode;
• a second insulating layer over the first insulating layer;
• a first oxide semiconductor layer over the second insulating layer;
• a second oxide semiconductor layer over the first oxide semiconductor layer;
• a third oxide semiconductor layer over the second oxide semiconductor layer;
• a third insulating layer over the third oxide semiconductor layer;
• and
• a second gate electrode over the third insulating layer,
• wherein in a channel width direction of the transistor, a bottom surface of the second oxide semiconductor layer is below a region of a bottom surface of the second gate electrode,
• wherein the region of the bottom surface of the second gate electrode does not overlap with the second oxide semiconductor layer and the first oxide semiconductor layer, and
• wherein when a level of the region of the bottom surface of the second gate electrode is regarded as a reference, a level of the bottom surface of the second oxide semiconductor layer from the reference is more than or equal to −10 nm to less than 0 nm.