Integrated Circuit Device With Low Threshold Voltage
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Liang Cheng, Ziwei Fang
Life of this patent
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Abstract
A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.
Claims20
A method of manufacturing a semiconductor device, comprising:
- providing a substrate having a first region and a second region;
- forming an n-type work function layer over the substrate in the first region but not in the second region;
- and
- forming a p-type work function layer, wherein the p-type work function layer includes a metal oxide, wherein the p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region, and wherein the p-type work function layer directly contacts the substrate in the second region.
A method to manufacture an integrated circuit (IC) device, comprising:
- forming a first opening in a first gate structure and a second opening in a second gate structure, wherein the first gate structure is disposed over a first fin structure and the second gate structure is disposed over a second fin structure;
- forming a gate dielectric layer in the first and the second openings;
- forming an n-type work function layer in the first and the second openings;
- removing the n-type work function layer in the second opening, but not in the first opening;
- forming a p-type work function layer in the first and the second openings, wherein the p-type work function layer includes a metal oxide;
- and
- forming a metal fill layer over the p-type work function layer in the first and the second openings.
A device comprising:
- a substrate including a semiconductor material;
- a first gate structure in an n-type region of the substrate;
- and
- a second gate structure in a p-type region of the substrate,
- wherein the first gate structure includes a p-type work function layer deposited over an n-type work function layer,
- wherein the second gate structure includes the p-type work function layer deposited over and directly contacting the substrate, and
- wherein the p-type work function layer includes ruthenium oxide (RuO2).
Dependencies are inferred from the claim text.