Semiconductor device and semiconductor memory device

A semiconductor device comprising:

• a N-type first well region of N-type, the first well region is provided in a surface region of a substrate;
• and
• a PMOS transistor provided in the first well region,
• wherein
• the PMOS transistor includes:
• a first gate insulating layer provided on the first well region;
• and
• a first gate electrode provided on the first gate insulating layer,
• the first gate electrode includes:
• a first semiconductor layer containing P-type semiconductor and carbon;
• a second semiconductor layer provided on the first semiconductor layer and containing P-type semiconductor;
• a first insulating layer provided on the second semiconductor layer;
• and
• a first conductive layer provided on the first insulating layer.

A semiconductor memory device comprising:

• a first well region of N-type and a second well region of P-type, the first well region and the second well region are provided in a surface region of a substrate;
• a PMOS transistor provided in the first well region;
• and
• an NMOS transistor provided in the second well region;
• a memory cell array provided above the PMOS transistor and NMOS transistor,
• wherein
• the PMOS transistor includes:
• a first gate insulating layer provided on the first well region;
• and
• a first gate electrode provided on the first gate insulating layer,
• the NMOS transistor includes:
• a second gate insulating layer provided on the second well region;
• and
• a second gate electrode provided on the second gate insulating layer,
• the first gate electrode includes:
• a first semiconductor layer of P-type;
• a first insulating layer provided on the first semiconductor layer;
• and
• a first conductive layer provided on the first insulating layer,
• the second gate electrode includes:
• an second semiconductor layer of N-type;
• a second insulating layer provided on the second semiconductor layer;
• and
• a second conductive layer provided on the second insulating layer, and
• a film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer,
• the memory cell array includes:
• select gate lines;
• word lines between the select gate lines;
• a memory pillar penetrating the select gate lines and the word lines;
• and
• a conductive layer contacting with the memory pillar.