Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices

A plurality of field effect transistor devices each having a gate structure, comprising:

• an interfacial layer on each semiconductor device channel of the plurality of field effect transistor devices, wherein a first set of the plurality of field effect transistor devices are n-type field effect transistor devices and a second set of field effect transistor devices are p-type field effect transistor devices;
• a dipole layer on the interfacial layer on each of a subset of the plurality of field effect transistor devices, wherein at least one of the dipole layers is on at least one of the n-type field effect transistor devices and at least another one of the dipole layers is on at least one of the p-type field effect transistor devices;
• a gate dielectric layer on each of the interfacial layers;
• a first work function layer on the gate dielectric layer on the first set of the plurality of field effect transistor devices;
• and
• a second work function layer on the gate dielectric layer on the second set of the plurality of field effect transistor devices, wherein the first work function layer is a work function material (WFM) different from the second work function layer.

A method of fabricating a plurality of field effect transistor devices each having a gate structure, comprising:

• forming a plurality of semiconductor device channels on a substrate;
• forming an interfacial layer on each of the plurality of semiconductor device channels;
• forming a gate dielectric layer on the interfacial layers;
• forming a conversion layer segment on the gate dielectric layer on a subset of the plurality of semiconductor device channels;
• forming a capping layer on each of the plurality of semiconductor device channels;
• forming a cover layer on the plurality of semiconductor device channels;
• and
• heat treating the conversion layer segments and plurality of semiconductor device channels to form a dipole layer between the interfacial layer and gate dielectric layer on the subset of the plurality of semiconductor device channels.