Integrated circuit device and method of manufacturing the same

An integrated circuit device comprising:

• a fin-type active region protruding from a substrate and extending in a first direction;
• a plurality of semiconductor patterns apart from an upper surface of the fin-type active region;
• a gate electrode surrounding the plurality of semiconductor patterns, the gate electrode extending in a second direction perpendicular to the first direction, the gate electrode comprising,
• a main gate electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extending in the second direction, and
• a sub-gate electrode between two the plurality of semiconductor patterns;
• a spacer structure disposed on a first sidewall and a second sidewall of the main gate electrode;
• and
• source/drain regions at respective sides of the plurality of semiconductor patterns and the source/drain regions respectively at a first side of the gate electrode and a second side of the gate electrode, and contacting a bottom surface of the spacer structure,
• wherein the main gate electrode comprises a round inclined surface inclined from a lower portion of the main gate electrode to at least one of the first sidewall of the main gate electrode or the second sidewall of the main gate electrode, the round inclined surface being inclined relative to a third direction perpendicular to an upper surface of the substrate.

An integrated circuit device comprising:

• a fin-type active region protruding from a substrate and extending in a first direction;
• a plurality of semiconductor patterns apart from an upper surface of the fin-type active region;
• a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode comprising,
• a main gate electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extending in the second direction, and
• a sub-gate electrode between two of the plurality of semiconductor patterns;
• a gate dielectric layer between the plurality of semiconductor patterns and the gate electrode;
• a spacer structure disposed on a first sidewall of the main gate electrode and a second sidewall of the main gate electrode;
• a pair of source/drain regions at respective sides of the plurality of semiconductor patterns, the pair of source/drain regions respectively at a first side of the gate electrode and a second side of the gate electrode, the pair of source/drain regions contacting a bottom surface of the spacer structure;
• and
• a contact plug electrically connected to the pair of source/drain regions,
• wherein a center portion of the main gate electrode has a first width in the first direction,
• a bottom portion of the main gate electrode has a second width in the first direction less than the first width,
• a space between center portions of the pair of source/drain regions has a third width in the first direction less than the second width, and
• the main gate electrode comprises a round inclined surface inclined from the bottom portion of the main gate electrode to at least one of the first sidewall of the main gate electrode or the second sidewall of the main gate electrode, the round inclined surface being inclined relative to a third direction perpendicular to an upper surface of the substrate.