US 2021/0082879 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

Claims12

Dependent claims

A semiconductor memory device comprising:

a memory cell above a substrate;
a first voltage generator between the substrate and the memory cell, the first voltage generator being configured to generate a first voltage to be supplied to the memory cell;
and
a second voltage generator between the substrate and the memory cell, the second voltage generator being configured to generate the first voltage and having a circuit configuration equivalent to the first voltage generator.

1 more element

A semiconductor memory device comprising:

a memory cell above a substrate;
a first circuit on a portion of the substrate between the substrate and the memory cell, the first circuit being configured to supply a voltage to the memory cell;
a test pattern on a central side of the substrate from the first circuit and including a pad;
and
an insulating layer on the pad,
wherein the pad is not electrically connected to an external terminal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/806,079Filed 2 Mar 2020

Priority

JP 2019-16937118 Sep 2019

Published

18 Mar 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10W 90/00
Package configurations
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims12