Backside contact for thermal displacement in a multi-wafer stacked integrated circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPing-Tzu Chen, Hsing-Chih Lin, Min-Feng Kao
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPing-Tzu Chen, Hsing-Chih Lin, Min-Feng Kao
Estimating the term…
In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.
A three-dimensional (3D) integrated circuit (IC) stack comprising:
An integrated circuit (IC) die comprising:
A method of forming an integrated circuit, the method comprising:
Dependencies are inferred from the claim text.