Back to results
US 2021/0082872 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorBongken Yu
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate.
Claims20
A semiconductor package comprising:
- a package substrate;
- a logic chip disposed on an upper surface of the package substrate and electrically connected to the package substrate;
- a heat sink disposed on an upper surface of the logic chip and configured to dissipate a heat generating from the logic chip;
- and
- a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate.
2 more elements
A semiconductor package comprising:
- a package substrate including a first pad and a second pad;
- a logic chip disposed on an upper surface of the package substrate and electrically connected to the first pad;
- a heat sink disposed on an upper surface of the logic chip and electrically insulated from the package substrate;
- and
- a memory chip disposed on an upper surface of the heat sink and electrically connected to the second pad.
2 more elements
A semiconductor package comprising:
- a substrate;
- a conductive layer disposed in the substrate;
- a first signal pad disposed on an upper surface of the substrate and connected to the conductive layer;
- a second signal pad disposed on the upper surface of the substrate and connected to the conductive layer;
- a first dummy pad disposed on the upper surface of the substrate;
- a second dummy pad disposed on the upper surface of the substrate;
- a heat transfer line connecting the first dummy pad and the second dummy pad;
- a logic chip disposed on the substrate and connected to the first dummy pad;
- a conductive bump interposed between the logic chip and the first signal pad;
- a first dummy bump interposed between the first dummy pad and the logic chip;
- a second dummy bump disposed on the second dummy pad;
- a heat sink disposed on an upper surface of the logic chip and including a heat transfer part connected to the second dummy bump;
- a memory chip disposed on an upper surface of the heat sink;
- and
- a conductive wire extending from the memory chip to the second signal pad.
12 more elements
Dependencies are inferred from the claim text.