Flexible provisioning of multi-tier memory

A system, comprising:

• a first memory chip in a string of memory chips of a memory;
• a second memory chip in the string of memory chips;
• and
• a third memory chip in the string of memory chips,
• wherein the first memory chip is directly wired to the second memory chip and is configured to interact directly with the second memory chip,
• wherein the second memory chip is directly wired to the third memory chip and is configured to interact directly with the third memory chip,
• wherein the first memory chip comprises a cache for the second memory chip,
• wherein the second memory chip comprises a buffer for the third memory chip, and
• wherein the second memory chip comprises logical-to-physical mapping for the third memory chip.

A system, comprising:

• a first memory chip in a string of memory chips of a memory;
• a second memory chip in the string of memory chips;
• a third memory chip in the string of memory chips;
• and
• a processor chip,
• wherein the first memory chip is directly wired to the second memory chip and is configured to interact directly with the second memory chip,
• wherein the second memory chip is directly wired to the third memory chip and is configured to interact directly with the third memory chip,
• wherein the processor chip is directly wired to the first memory chip and is configured to interact directly with the first memory chip, and
• wherein the processor chip is configured to configure a cache in the first memory chip for the second memory chip.