Instructions for vector multiplication of signed words with rounding

A method comprising:

• fetching, by fetch circuitry, a vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier;
• decoding, by decode circuitry, the fetched vector multiplication instruction;
• and
• executing, by execution circuitry, the decoded vector multiplication instruction, on each of a plurality of pairs of corresponding fixed-sized elements of the identified first and second sources, to:
• generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size;
• and
• generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

A system comprising:

• a memory;
• and
• a processor comprising:
• means for fetching the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier;
• means for decoding the fetched vector multiplication instruction;
• and
• means for executing the decoded vector multiplication instruction, on each of a plurality of pairs of corresponding fixed-sized elements of the identified first and second sources, to:
• generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size;
• and
• generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.