Vacuum Packaged Infrared Sensor Arrays

A method for fabricating a vacuum packaged infrared sensor array comprising two stages:

• preparing an infrared sensor array silicon substrate and preparing a lid silicon substrate, wherein the said preparing of an infrared sensor array silicon substrate comprises the following fabrication steps:
• providing a p-type silicon substrate;
• creating a 200 to 300 nm thick silicon nitride HF resistive mask pattern by low temperature vapor chemical deposition (LPCVD) and conducting a photolithography process;
• conducting anodization in a HF solution to grow a 20 to 50 μm thick porous silicon layer in said silicon substrate;
• conducting low temperature oxidization of the said porous silicon layer at 350° C. in oxygen for 30 min;
• removing the residue silicon nitride layer by etching;
• depositing both a 100 nm thick polysilicon layer and a 500 nm thick silicon nitride layer over the surface of the said silicon substrate by plasma enhanced chemical vapor deposition (PECVD);
• depositing a 100 to 200 nm thick amorphous silicon layer over the surface of the said silicon substrate by LPCVD at 475° C.;
• pattering the said amorphous silicon layer to create an amorphous silicon active area for a thermopile, an amorphous silicon active area for a field-effect transistor (FET) and an amorphous silicon active area for several buried amorphous silicon interconnection bridges by a photolithography process;
• conducting recrystallization of the said amorphous silicon active areas to form recrystallized amorphous silicon active areas with larger grain size;
• conducting thermal oxidization of the said recrystallized amorphous silicon areas to grow a 70-100 nm thick silicon dioxide layer on the said recrystallized amorphous silicon active areas;
• depositing a 300 nm polysilicon layer by LPCVD over the surface of the said silicon substrate at 650° C.;
• pattering the said polysilicon layer to create a polysilicon element for an infrared absorber and a polysilicon gate for the FET by photolithography process;
• conducting n+ such as phosphorus ion implantation to form n+ recrystallized amorphous silicon legs for the thermopile, a n+ recrystallized amorphous silicon drain, a n+ recrystallized amorphous silicon source and a n+ polysilicon gate for the FET;
• conducting p+ such as boron ion implantation to form p+ recrystallized amorphous silicon legs for the thermopile and p+ recrystallized amorphous silicon interconnection bridges;
• annealed at 950° C. in nitrogen for 30 min;
• depositing a 1100 nm silicon dioxide layer by PECVD;
• conducting a photolithography process;
• conducting a plasma passivation treatment on the recrystallized amorphous silicon drain and source of the said FET;
• depositing a 200 nm thick titanium layer and conducting a photolithography process;
• depositing a 1000 nm thick aluminum layer by sputtering and conducting a photolithography process;
• depositing a 850 nm thick high density plasma (HDP) silicon nitride layer over the surface of the said silicon substrate;
• producing a seal ring consisting of Ti/Pt/Au on the round edge of the said infrared sensor array;
• creating an etching window in the said HDP silicon nitride layer down to the said porous silicon layer;
• etching the said porous silicon layer in a diluted KOH solution to create a cavity replacing the said porous silicon layer and release the stack layer over the said porous silicon layer which results in a membrane over the said cavity and finally finish the fabrication process of the said infrared sensor array silicon substrate and the said preparing of a lid silicon substrate comprises the following fabrication steps:
• providing a lid silicon substrate;
• growing a 20 to 50 μm thick central porous silicon layer and a 20 to 50 μm thick edge porous silicon layer in an area sized equal to the said infrared sensor array;
• creating a seal ring consisting of Ti/Pt/Au/Ge/Au on the round edge of the said central porous silicon layer;
• removing Si-H species on the pore walls of the said porous silicon layers by heating up to 350° C. in vacuum;
• loading the said infrared sensor array silicon substrate and the said lid substrate into a vacuum bonding system;
• before bonding the said vacuum system is pumped from an atmosphere to vacuum and then filled with oxygen back to the atmosphere for 2 to 3 times;
• conducting eutectic bonding of the said lid silicon substrate and the said sensor silicon substrate in vacuum at 350° C. to 450° C. so as to oxidize the said porous silicon layers and consume the residue oxygen in the chamber sandwiched between the said lid silicon substrate and the said infrared sensor array silicon substrate;
• cutting the said lid silicon substrate down to the said edge porous silicon layer;
• etching the said edge porous silicon layer and etching the said HDP silicon nitride layer to real the said aluminum bon pads so as to finish the fabrication process for the said vacuum packaged only silicon substrate infrared sensor array.