US 2021/0066493 A1 · MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.

Claims15

Dependent claims

A memory device, comprising:

a gate stacking structure, disposed over a substrate;
a first insulating layer, covering a top surface and a sidewall of the gate stacking structure;
a second insulating layer, covering a surface of the first insulating layer, wherein a top corner region of the gate stacking structure is covered by the first insulating layer and the second insulating layer;
and
a first spacer, located on the sidewall of the gate stacking structure, and covering a surface of the second insulating layer, wherein a topmost end of the first spacer is lower than a topmost surface of the second insulating layer, the second insulating layer has an extending portion extending outwardly from the sidewall of the gate stacking structure along a surface of the substrate, and a terminal surface of the extending portion of the second insulating layer is substantially coplanar with a surface of the first spacer.

2 more elements

A manufacturing method of a memory device, comprising:

forming a gate stacking structure over a substrate;
sequentially forming a first insulating layer, a second insulating layer and a mask material layer over the substrate to cover the gate stacking structure;
performing an ion implantation process on the mask material layer, to form a doped portion in the mask material layer, wherein the doped portion caps on a top portion of the gate stacking structure;
performing a first patterning process on the mask material layer by using the doped portion as a shadow mask, to remove a bottom portion of the mask material layer extending along a surface of the substrate;
and
performing a second patterning process to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure, wherein a remained portion of the mask material layer forms a first spacer.

3 more elements

Dependencies are inferred from the claim text.

Memory device and manufacturing method thereof

Life of this patent

Memory device and manufacturing method thereof

Life of this patent

Abstract

Claims15