Structure and method for bi-layer self-aligned contact

A method of forming an integrated circuit structure, comprising:

• forming a gate stack on a semiconductor substrate with a gate spacer on a sidewall of the gate stack and an etch stop layer on a sidewall of the gate spacer and an interlayer dielectric (ILD) layer surrounding the gate stack, the gate spacer and the etch stop layer;
• etching back the gate stack to a first height, resulting in a trench;
• etching the gate spacer to a second height greater than the first height;
• depositing a first dielectric layer in the trench;
• recessing the first dielectric layer;
• removing a portion of the etch stop layer above the first dielectric layer such that the etch stop layer has a third height greater than the second height;
• and
• forming a second dielectric layer on the first dielectric layer and the etch stop layer, the second dielectric layer laterally contacting sidewalls of the ILD layer.

A semiconductor structure, comprising:

• a gate stack disposed on a semiconductor substrate;
• a spacer disposed on a sidewall of the gate stack;
• an etch stop layer disposed on a first sidewall of the gate spacer;
• a first dielectric layer disposed on the gate stack and contacting the gate spacer and the etch stop layer, the first dielectric layer having a T-shape;
• and
• a second dielectric layer disposed on the first dielectric layer and contacting the etch stop layer, the second dielectric layer being wider than the first dielectric layer.