Integrated Assemblies, and Methods of Forming Integrated Assemblies

A method of forming an integrated assembly, comprising:

• forming a first stack over a metal-containing structure;
• the first stack comprising a first layer, a second layer over the first layer, and a third layer over the second layer;
• forming a first opening to extend through the first stack;
• lining the first opening with a protective first material, and then filling the lined first opening with a second material;
• after filling the lined first opening, forming a second stack over the first stack;
• the second stack having alternating first and second levels;
• the first levels comprising third material and the second levels comprising fourth material;
• the fourth material being insulative;
• forming a second opening to pass through the second stack and to the second material within the first opening;
• extending the second opening through the second material and to the protective first material;
• forming channel material within the extended second opening;
• forming a third opening to pass through the second stack, through the third layer, and to the second layer;
• lining sidewall surfaces of the third opening with protective fifth material;
• removing the second layer selectively relative to the first and third layers, and selectively relative to the protective fifth material;
• the removal of the second layer forming a conduit;
• forming conductively-doped semiconductor material within the conduit;
• out-diffusing dopant from the conductively-doped semiconductor material into the channel material, the out-diffused dopant migrating upwardly to at least a lowermost first level of the second stack;
• and
• replacing at least some of the third material with conductive material to form the first levels into conductive levels.

A method of forming an integrated assembly, comprising:

• forming a first stack over a metal-containing structure;
• the first stack comprising a first layer, a second layer over the first layer, and a third layer over the second layer;
• the first and third layers comprising conductively-doped silicon;
• the second layer comprising silicon dioxide;
• forming a first opening to extend through the first stack;
• forming a liner within the first opening to line the first opening;
• forming tungsten within the lined first opening;
• forming a second stack over the first stack;
• the second stack having alternating first and second levels;
• forming a second opening to pass through the second stack and to the tungsten;
• extending the second opening through the tungsten;
• forming first semiconductor material within the extended second opening;
• forming a third opening to pass through the second stack, through the third layer, and to the second layer;
• lining sidewall surfaces of the third opening with protective material;
• removing the silicon dioxide of the second layer to form a conduit;
• forming conductively-doped second semiconductor material within the conduit;
• out-diffusing dopant from the conductively-doped second semiconductor material into the first semiconductor material, the out-diffused dopant extending upwardly to at least one of the first levels;
• forming conductive material within the first levels;
• and
• forming insulative material within the third opening.

An integrated structure, comprising:

• a source structure comprising conductively-doped semiconductor material;
• vertically-stacked conductive levels over the source structure;
• upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;
• channel material extending vertically along the memory cell levels and the select device level;
• a region of the channel material under the select device level being a lower region of the channel material;
• one or more memory cell materials between the channel material and the vertically-stacked conductive levels;
• the one or more memory cell materials being along said lower region of the channel material;
• a first liner region between the memory cell materials and the conductively-doped semiconductor material of an upper portion of the conductively-doped semiconductor material of the source structure;
• a second liner region between the memory cell materials and the conductively-doped semiconductor material of a lower portion of the conductively-doped semiconductor material of the source structure the first and second liner regions each comprising metal nitride;
• and
• a gap between the first and second liner regions.