Signal line patterning for standard cells

A method of fabricating an integrated circuit, comprising:

• forming a hard mask (110, 103) on a substrate (102);
• forming a layer of dielectric material (150) on the hard mask;
• forming, with a first photolithography process, a plurality of first spacers (114) on the layer of dielectric material and separated from each other by first gaps (122) defining a pattern for first and second supply tracks (104A, 104B) of a unit cell and first and second signal lines (106A, 106D) of the unit cell between the first and second supply tracks;
• and
• forming a heavily doped region (154) in the layer of dielectric material between two of the first spacers, wherein second gaps (155) between the heavily doped region and the two of the first spacers define a pattern for third and fourth signal lines of the unit cell between the first and second signal lines.

A method of fabricating an integrated circuit, comprising:

• forming a plurality of first spacers (114) on a hard mask (110, 103) positioned on a substrate (102), the first spacers defining first openings (122) corresponding to a pattern for first and second supply tracks (104A, 104B) of a unit cell and first and second signal lines (106A, 106D) of the unit cell between the first and second supply tracks;
• forming two second spacers (160) between two of the first spacers, wherein the second spacers are selectively etchable with respect to the first spacers;
• forming a third spacer (162) on the hard mask in a gap between the second spacers;
• and
• defining second openings (163) between the third spacer and the two of the first spacers by removing the second spacers, wherein the second openings define a pattern for third and fourth signal lines (106A, 106D) of the unit cell between the first and second supply tracks.