Temperature dependent impedance mitigation in non-volatile memory

A non-volatile storage apparatus, comprising:

• a temperature sensor configured to sense temperature;
• a NAND string comprising a first select transistor, a second select transistor, and data memory cells between the first select transistor and the second select transistor;
• a bit line connected to the first select transistor;
• a source line connected to the second select transistor;
• a first select line connected to the first select transistor;
• a second select line connected to the second select transistor;
• and
• a control circuit connected to the bit line, the source line, the first select line;
• the second select line and the temperature circuit;
• the control circuit is configured to erase the data memory cells by applying voltage pulses to the bit line, the source line, the first select line and the second select line to cause a first gate induced drain leakage (GIDL) current from the first select transistor into the data memory cells and a second GIDL current from the second select transistor into the data memory cells, the first GIDL current and the second GIDL current cause the data memory cells to change threshold voltages;
• the control circuit is configured to adjust at least one of the first GIDL current and the second GIDL current based a temperature sensed by the temperature sensor.