System, Apparatus And Method For Segmenting A Memory Array

An integrated circuit comprising:

• a register file containing multiple segments with heterogeneous power consumption levels;
• and
• one or more processing cores coupled to the register file,
• wherein more frequently-accessed data from the one or more processing cores is assigned to lower-power register file segments, and
• wherein less frequently-accessed data from the one or more processing cores is assigned to higher-power register file segments.

An integrated circuit comprising:

• one or more cores;
• a register file coupled to the one or more cores, wherein the register file comprises a plurality of storage segments including a first storage segment and a second storage segment;
• and
• a selection circuit coupled to the register file, wherein the first storage segment is closer to the selection circuit than the second storage segment, and a read operation to the first storage segment is to consume less power than a read operation to the second storage segment.

An integrated circuit comprising:

• a register file containing multiple segments with heterogeneous performance levels;
• and
• one or more processing cores coupled to the register file,
• wherein more frequently-accessed data from the one or more processing cores is to be assigned to higher performance register file segments, and
• wherein less frequently-accessed data from the one or more processing cores is to be assigned to lower performance register file segments.