A shift register unit, comprising a display circuit, wherein the display circuit is configured to provide a drive scanning signal to a corresponding gate line in a display phase, and the display circuit comprises a first control circuit and a first bias control circuit;
- the first control circuit is connected to a first node, and is configured to perform noise reduction on an output terminal of the display circuit under control of a level of the first node;
- and
- the first bias control circuit is connected to a first clock signal terminal, a first reference voltage signal terminal, and the first node, and is configured to transmit a first reference voltage signal provided by the first reference voltage signal terminal to the first node under control of a first clock signal provided by the first clock signal terminal, thereby turning off the first control circuit by controlling the level of the first node in a non-display phase.