Distributed multi-die protocol application interface

A method comprising:

• communicating data between an input/output (I/O) die and a processor die over a communication bus comprising a plurality of channels and a clock signal line,
• wherein the I/O die comprises a first bus interface coupled to the communication bus, a second bus interface coupled to a memory and an on-die interconnect coupling the first bus interface to the second bus interface,
• wherein the processor die comprises a processor and a third bus interface, the third bus interface coupling the processor die to the first bus interface over the communication bus, and
• wherein the TO die is configured as an interface between the processor and the memory, and
• wherein the plurality of channels of the communication bus comprise a first subplurality of unidirectional channels from the first bus interface to the third bus interface and a second subplurality of unidirectional channels from the third bus interface to the first bus interface;
• transmitting source synchronous data comprising a plurality of data signals from the first bus interface to the third bus interface using the communication bus;
• synchronizing, by the third bus interface, the plurality of data signals of the source synchronous data by latching the received source synchronous data using a clock signal transmitted from the first bus interface over the clock signal line;
• and
• separately setting a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect,
• wherein in a first configuration, the clock frequency associated with the second bus interface is different from the clock frequency associated with the on-die interconnect, and in a second configuration, the clock frequency associated with the on-die interconnect and the clock frequency associated with the second bus interface are the same.

A system comprising:

• a memory device;
• a communication bus comprising a plurality of channels and a clock signal line;
• an input/output (TO) die comprising:
• a first bus interface coupled to the communication bus,
• a second bus interface to couple the IO die to the memory device,
• an on-die interconnect to couple the first bus interface to the second bus interface;
• and
• a processor die comprising:
• a third bus interface to couple the processor die to the first bus interface over the communication bus, and
• a processor to exchange data with the IO die over the communication bus, wherein the IO die is configured as an interface between the processor and the memory device, and
• wherein the plurality of channels comprise a first subplurality of unidirectional channels from the first bus interface to the third bus interface and a second subplurality of unidirectional channels from the third bus interface to the first bus interface, the first bus interface to transmit source synchronous data comprising a plurality of data signals to the third bus interface using the communication bus,
• wherein the third bus interface comprises circuitry that synchronizes the plurality of data signals of the source synchronous data by latching the received source synchronous data using a clock signal transmitted from the first bus interface over the clock signal line,
• wherein a clock frequency associated with the second bus interface and a clock frequency associated with the on-die interconnect are separately settable, and
• wherein in a first configuration, the clock frequency associated with the second bus interface is different from the clock frequency associated with the on-die interconnect, and in a second configuration, the clock frequency associated with the on-die interconnect and the clock frequency associated with the second bus interface are the same.