Memory system including heterogeneous memories, computer system including the memory system, and data management method thereof

A computer system, comprising:

• a central processing unit (CPU);
• and
• a memory system electrically coupled to the CPU through a system bus,
• wherein the memory system comprises:
• a first memory device having a first memory that includes a plurality of access management regions and a first access latency, each of the access management regions including a plurality of pages, the first memory device configured to detect a hot access management region having an access count that reaches a preset value from the plurality of access management regions, and detect one or more hot pages included in the hot access management region;
• and
• a second memory device having a second access latency different from the first access latency of the first memory device,
• wherein data stored in the one or more hot pages is migrated to the second memory device.

A data management method for a computer system comprising a central processing unit (CPU) and first and second memory devices, the method comprising:

• transmitting, by the CPU, a hot access management region check command to the first memory device for checking whether a hot access management region is present in a first memory of the first memory device;
• transmitting, by the first memory device, a first response or a second response to the CPU in response to the hot access management region check command, the first respond including information related to one or more hot pages in the hot access management region, the second response indicating that the hot access management region is not present in the first memory;
• and
• transmitting, by the CPU, a data migration command for exchanging hot data, stored in the one or more hot pages of the first memory, with cold data in a second memory of the second memory device, to the first and second memory devices when the first response is received from the first memory device, the first memory device having longer access latency than the second memory device.

A memory device, comprising:

• a non-volatile memory;
• and
• a controller configured to control an operation of the non-volatile memory,
• wherein the controller is configured to divide the non-volatile memory into a plurality of access management regions, each of which comprises a plurality of pages, include an access count table for storing an access count of each of the plurality of access management regions and a plurality of bit vectors configured with bits corresponding to a plurality of pages included in each of the plurality of access management regions, store an access count of an accessed access management region of the plurality of access management regions in a space of the access count table corresponding to the accessed access management region when the non-volatile memory is accessed, and set, as a first value, a bit corresponding to an accessed page among bits of a bit vector corresponding to the accessed access management region.