Arithmetic circuit, and neural processing unit and electronic apparatus including the same

A neural processing unit, comprising:

• a multiplier receiving an n-bit first signal and an m-bit second signal, and outputting a value generated by multiplying the first signal by the second signal;
• an input buffer latching each of a plurality of input signals, sequentially input from the multiplier, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals according to each of the plurality of input signals;
• a first ripple carry adder (RCA) performing a first part of an accumulation operation accumulating on each of the plurality of first addition signals to generate a first sum signal and a carry;
• a first flip-flop;
• a second RCA performing a second part of the accumulation operation on each of the plurality of second addition signals and an output of the first flip-flop to generate a second sum signal, wherein the first RCA latches the carry in the first flip-flop after performing the accumulation operation;
• and
• an output buffer latching the first sum signal and the second sum signal, and outputting a total sum signal representing a sum of the plurality of input signals.

An electronic device, comprising:

• a memory storing data;
• and
• a neural processing unit including an arithmetic circuits, and performing machine learning using the data,
• wherein the arithmetic circuit comprises:
• an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals according to each of the plurality of input signals;
• a first ripple carry adder (RCA) performing a first part of an accumulation operation on the plurality of first addition signals to generate a first sum signal and a carry;
• a flip-flop;
• a second RCA performing a second part of the accumulation operation one the plurality of second addition signals and an output of the flip-flop to generate a second sum signal, wherein the first RCA latches the carry in the first flip-flop after performing the accumulation operation;
• and
• an output buffer latching the first sum signal and the second sum signal, and outputting a total sum signal.