Apparatuses and methods to mask write operations for a mode of operation using ecc circuitry

A memory comprising:

• a pair of main input/output (I/O) lines coupled to a memory cell array;
• a pull-up circuit configured to provide a first voltage to a selected first one of the pair of main I/O lines;
• a pull-down circuit configured to provide a second voltage to a selected second one of the pair of main I/O lines;
• and
• a write driver circuit configured to receive a bit of corrected read data retrieved from the memory cell array and a bit of write data, wherein the write driver circuit is configured to disable the pull-up and pull-down circuits in response to the bit of corrected read data matching the bit of write data, wherein the write driver circuit is configured to enable the pull-up circuit to provide the first voltage to the selected first one of the pair of main I/O lines and to enable the pull-down circuits to provide the second voltage to the selected second one of the pair of main I/O lines in response to the bit of corrected read data being different than the bit of write data.

A method comprising:

• receiving data corresponding to a write command received via data terminals of a semiconductor device;
• combining the data corresponding to the write command with a first subset of corrected read data retrieved from a memory cell array of the semiconductor device to provide write data;
• masking, via a write driver circuit, a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data;
• and
• performing a write operation for a second bit of the write data that corresponds to the data received via the data terminals.