US 2021/0064076 A1Published application

Low power clock gate circuit

AssigneeIntel Corporation

InventorsGururaj Shamanna, Mitesh Goyal, Jagadeesh Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu

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Abstract

A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.

Claims20

Dependent claims

An apparatus comprising:

a first transmission gate to receive an input signal, wherein the first transmission gate is controllable by clock and a complementary of clock;
a memory circuitry comprising a first inverter and a second inverter coupled in a ring, wherein the memory circuitry is coupled to the first transmission gate, wherein the second inverter is controllable by at least the complementary of the clock;
a second transmission gate coupled to the first inverter and to receive the complementary of clock, wherein the second transmission gate is controllable by an output of the first inverter;
a keeper device coupled to the second transmission gate, wherein the keeper device is controllable by the output of the first inverter;
and
a third inverter coupled to the keeper device and the second transmission gate, wherein and output of the third inverter is to control the second inverter.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/557,860Filed 30 Aug 2019
Published: 4 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency
H03K 3/012
Details: modifications of generator to improve response time or to decrease power consumption

Family

US 10,996,709 B2Related patent
US 2021/0064076 A1This patent

From the US filing history. Foreign family members aren’t listed.

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