Semiconductor device
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsYuki Watanabe, Toshiaki Dozaka
Life of this patent
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Abstract
According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.
Claims20
A semiconductor device comprising:
- a first scan chain and a second scan chain each including a plurality of cascaded flip-flops;
- a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
- and
- a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock, wherein
- the plurality of flip-flops are arranged along the second direction.
A semiconductor device comprising:
- a first scan chain and a second scan chain that each includes a plurality of cascaded flip-flops;
- a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
- a first signal line coupled to a clock terminal of the first scan chain;
- a second signal line coupled to a clock terminal of the second scan chain;
- a first delay element coupled between the first scan chain and the second scan chain;
- a second delay element coupled between the first signal line and the second signal line;
- and
- a clock control circuit that supplies a clock to the first signal line, wherein
- the plurality of flip-flops are arranged along the second direction.
A semiconductor device comprising:
- a first scan chain and a second scan chain that each includes a plurality of cascaded flip-flops;
- a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
- a latch circuit coupled between the first scan chain and the second scan chain;
- a first signal line coupled to a clock terminal of the first scan chain;
- a second signal line coupled to a clock terminal of the second scan chain and a clock terminal of the latch circuit;
- a delay element coupled between the first signal line and the second signal line;
- and
- a clock control circuit that supplies a clock to the first signal line, wherein
- the plurality of flip-flops are arranged along the second direction.
Dependencies are inferred from the claim text.