Clock crossing interface for integrated circuit generation
AssigneeSiFive, Inc.
InventorsHenry Cook, Wesley Waylon Terpstra, Ryan MacDonald
Life of this patent
Estimating the term…
Loading patent…
AssigneeSiFive, Inc.
InventorsHenry Cook, Wesley Waylon Terpstra, Ryan MacDonald
Estimating the term…
Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.
A method comprising:
A system comprising:
A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
Dependencies are inferred from the claim text.