Auto-calibration circuit for pulse generating circuit used in resonating circuits
AssigneeRezonent Microchips Pvt. Ltd.
InventorsIgnatius Bezzam, Neelam Rawat
Life of this patent
Estimating the term…
Abstract
Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.
Claims10
An auto-calibration circuit (206) for calibrating a circuit fabricated on Metal-Oxide Semiconductors (MOS) technology providing required calibration to improve the performance of the circuit, wherein said auto-calibration circuit (206) comprises:
- an inverter block (302) that comprises a P-type Metal Oxide Semiconductor (PMOS) (312) and a N-type Metal Oxide Semiconductor (NMOS) (314);
- one or more gated inverters (304A-304N) that obtain first inputs Bn and Bp from Digital Memory Counters of the circuit, wherein the one or more gated inverters (304A-304N) comprises a plurality of PMOS and a plurality of NMOS;
- a first comparator (306) that is connected with the one or more gated inverters (304A-304N) that obtains a second input from at least one of the inverter block (302) or the one or more gated inverters (304A-304N);
- a NMOS gate (320) that is connected with a capacitor (316) and an XOR gate (318) to charge the capacitor (316) using a XOR signal (n1x) from the XOR gate (318), wherein the XOR gate (318) generates the XOR signal when the XOR gate (318) is connected with the first comparator (306);
- a second comparator (308) that obtains input from at least one of a voltage divider (310) or a capacitor (316);
- a PMOS counter that increases the count values when output values of the second comparator (308) and the XOR gate (318) are high, wherein the count values of the PMOS counter enables the plurality of PMOS of the one or more gated inverters (304A-304N);
- and
- a NMOS counter that increases the count values when the output value of the second comparator (308) is low and the output value of the XOR gate (318) is high, wherein the count values of the NMOS counter enables the plurality of NMOS of the one or more gated inverters (304A-304N) to provide required calibration to the circuit.
A method for calibrating the pulse widths of a pulse generator (102) circuit using auto-calibration circuit (206), the method comprising
- generating a pulse to turn on a NMOS switch (320) using a first comparator (318);
- allowing a capacitor (316) to charge based on an input signal using the NMOS switch (320);
- generating a second comparator output (nvx) based on the input received from the capacitor (316) and a resistance divider (310) using a second comparator (308);
- and
- generating control bits using one or more gated inverters (304A-304N) for calibrating the pulse widths of a pulse generator (102).
Dependencies are inferred from the claim text.