Optimizing software-directed instruction replication for gpu error detection

A system comprising:

• a multi-processor comprising a first execution lane, a second execution lane, and a third execution lane;
• logic to interleave execution by the multi-processor of duplicated instructions of a first thread in the first execution lane with execution by the multi-processor of original instructions of a second thread in the second execution lane;
• and
• logic to interleave execution by the multi-processor of duplicated instructions of the second thread with execution by the multi-processor of original instructions of a third thread in the third execution lane.

A parallel processor comprising:

• logic to duplicate original instructions of a first thread executing in a first execution lane of a processor into duplicate instructions and to interleave the duplicate instructions between original instructions of a second thread executing in a second execution lane of the processor;
• logic to accumulate first results for the original instructions of the first thread;
• logic to accumulate second results for the duplicate instructions;
• logic to perform a test, subsequent to an exit point of the first thread, based on the first results and the second results;
• and
• logic to raise an alert if the test meets a condition.

A thread execution method comprising:

• in one or more of a a self-driving car, a robot, or an imaging system comprising at least one processor:
• executing original instructions of a first thread in a first execution lane of the at least one processor;
• and
• interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the at least one processor.

A data center comprising:

• a plurality of computer systems, each comprising at least one multi-processor;
• and
• logic to configure the multi-processor of one or more of the computer systems to:
• execute original instructions of a first thread in a first execution lane of the multi-processor;
• and
• interleave execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the multi-processor.