Memory interface, data storage device including the same and operating method thereof
AssigneeSK hynix Inc.
InventorHo Jung YUN
Life of this patent
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Abstract
A memory interface may include: a transceiver module configured to exchange signals with a plurality of dies; and an input/output (I/O) rate controller configured to calculate per-signal-interval ratios of each of the dies by monitoring signals transmitted to, and received from, each of the dies, select a first die whose operating time is relatively slow and a second die whose operating time is relatively fast, among the plurality of dies, using the calculated per-signal-interval ratios, and provide the transceiver module with information for adjusting data interval ratios for each of the first and second dies.
Claims21
A memory interface for interfacing a controller and a memory device including a plurality of dies, the memory interface comprising:
- a transceiver module configured to exchange signals with the plurality of dies;
- and
- an input/output (I/O) rate controller configured to:
- calculate per-signal-interval ratios of each of the dies by monitoring signals transmitted to, and received from, each of the dies,
- select a first die whose operating time is relatively slow and a second die whose operating time is relatively fast, among the plurality of dies, using the calculated per-signal-interval ratios, and
- provide the transceiver module with information for adjusting data interval ratios for each of the first and second dies.
A data storage device comprising:
- a nonvolatile memory device comprising a plurality of memory chips;
- and
- a controller configured to:
- calculate per-signal-interval ratios of each of the memory chips by monitoring signals transmitted to, and received from, the plurality of memory chips, respectively,
- select a first memory chip whose operating time is the slowest and a second memory chip whose operating time is the fastest, among the plurality of memory chips, using the calculated per-signal-interval ratios, and
- adjust data interval ratios for each of the first and second memory chips.
An operating method of a controller for controlling a memory device including plural chips operably coupled to the controller through respective channels, the operating method comprising:
- identifying busy intervals of the respective chips by snooping signals transferred through the channels for a set time interval;
- and
- performing a signal transfer rate adjusting operation of increasing a signal transfer rate of a first channel and decreasing a signal transfer rate of a second channel, among the channels,
- wherein the first channel corresponds to a chip having a relatively long busy interval and the second channel corresponds to a chip having a relatively short busy interval, among the chips.
Dependencies are inferred from the claim text.