Adapting memory block pool sizes using hybrid controllers

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to:

• determine, by the processor, whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue;
• in response to determining that the number of blocks included in the first RTU queue is in the first range of the first RTU queue, determine, by the processor, whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue;
• in response to determining that the number of blocks included in the second RTU queue is not in the second range of the second RTU queue, relocate, by the processor, valid data from one of the blocks in a first pool which corresponds to the first RTU queue;
• erase, by the processor, the block in the first pool;
• and
• transfer, by the processor, the block from the first pool to the second RTU queue which corresponds to a second pool,
• wherein the blocks in the first pool are configured in single-level cell (SLC) mode,
• wherein the blocks in the second pool are configured in multi-bit-per-cell mode.

A system, comprising:

• a plurality of non-volatile random access memory (NVRAM) blocks configured to store data;
• and
• a processor and logic integrated with and/or executable by the processor, the logic being configured to:
• determine, by the processor, whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue;
• in response to determining that the number of blocks included in the first RTU queue is in the first range of the first RTU queue, determine, by the processor, whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue;
• in response to determining that the number of blocks included in the second RTU queue is not in the second range of the second RTU queue, relocate, by the processor, valid data from one of the blocks in a first pool which corresponds to the first RTU queue;
• erase, by the processor, the block in the first pool;
• and
• transfer, by the processor, the block from the first pool to the second RTU queue which corresponds to a second pool,
• wherein the blocks in the first pool are configured in single-level cell (SLC) mode,
• wherein the blocks in the second pool are configured in multi-bit-per-cell mode.