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US 2020/0404775 A1Published application
Printed circuit boards with non-functional features
AssigneeDell Products L.P.
InventorsUmesh Chandra, Bhyrav M. Mutnury
Life of this patent
Estimating the term…
Abstract
A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).
Claims20
A printed circuit board (PCB) comprising:
- a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board;
- one or more holes each of which passes through one or more of the layers;
- and
- one or more conductive vias each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;
- wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the one or more vias, wherein an interface between each NFF and the corresponding via does not completely laterally surround the corresponding via.
- wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.
3 more elements
A printed circuit board (PCB) comprising:
- a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board;
- one or more holes each of which passes through one or more of the layers;
- and
- one or more conductive vias each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;
- wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the one or more vias, but not completely laterally surrounding the corresponding via;
- wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.
3 more elements
A method for manufacturing a printed circuit board (PCB), the method comprising:
- forming a plurality of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board, wherein each of one or more of the layers comprises one or more conductive features each of which comprises one or more non-functional features (NFFs);
- then
- attaching the layers to each other to form a stack of the layers;
- then
- forming one or more holes through one or more of the layers, wherein each of one or more of the holes has a boundary shared with at least one NFF that does not completely laterally surround the hole;
- then
- forming one or more conductive vias comprising a portion of the circuitry and passing through one or more of the layers, each via being formed in a corresponding one of the one or more holes, wherein the boundary of each NFF physically contacts a via formed in the hole sharing the boundary with the NFF;
- wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.
5 more elements
Dependencies are inferred from the claim text.