Dynamic driver voltage headroom adjustment

A circuit, comprising:

• a processing element configured to:
• receive a digital input signal;
• partition the digital input signal to generate a control signal, comprising:
• while the digital input signal has a value in a first value range, mapping the digital input signal to a first value range;
• and
• while the digital input signal has a value in a second value range, mapping the digital input signal to a second value range;
• and
• generate a partition control signal in accordance with the digital input signal;
• and
• a driver configured to drive a light-emitting diode by:
• receiving the control signal from the processing element;
• controlling a digital-to-analog converter (DAC) to generate a current for the light-emitting diode, responsive to the digital input signal and a reference current, with a first voltage headroom (VHR) value responsive to the partition control signal while the digital input signal has the value in the first value range;
• and
• controlling the DAC to generate the current to the light-emitting diode with a second VHR value responsive to the partition control signal while the digital input signal has the value the second value range.

A system, comprising:

• a power regulator comprising an input adapted to be coupled to a power source, and the power regulator comprising an output coupled to a first node;
• a processing element configured to generate a digital control signal and a partition control signal according to a brightness code;
• a driver, comprising:
• a digital-to-analog converter (DAC) comprising a first terminal coupled to the output of power regulator, and a second terminal, and the DAC configured to receive the digital control signal from the processing element;
• a first transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal, and a gate terminal;
• a second transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the drain terminal of the first transistor, and a gate terminal;
• a switch coupled between the gate terminal of the second transistor and the gate terminal of the first transistor, the switch configured to receive the partition control signal from the processing element;
• a first current mirror coupled to the drain terminal of the first transistor and to the second terminal of the DAC;
• a second current mirror coupled to the first current mirror;
• and
• a third transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal coupled to the gate terminal of the first transistor;
• and
• a light-emitting diode coupled between the second terminal of the DAC and a ground terminal.