US 2020/0403941 A1 · DATA PACKET PROCESSING METHOD AND APPARATUS, AND DEVICE

Abstract

Embodiments of the present invention disclose a data packet processing method and apparatus, and a device. The method includes: if a first data packet is received, determining a first cache queue that is in the first buffer and that is used to store the first data packet; buffering the first data packet in the second buffer if a state of the first cache queue is an invalid state, where a data amount of the first data packet is less than the capacity of the second buffer, and the state of the first cache queue is set to the invalid state when a current data amount of the first buffer reaches the capacity of the first buffer; and if a data amount of the second buffer reaches the capacity of the second buffer, sending all data packets that are in the second buffer to a control plane device.

Claims14

Dependent claims

A data packet processing method, wherein the method is applied in a forwarding plane device, the forwarding plane device comprises a first buffer and a second buffer, the first buffer comprises at least one cache queue, and the method comprises:

when a first data packet is received, determining a first cache queue that is in the first buffer and that is used to store the first data packet;
buffering the first data packet in the second buffer when a state of the first cache queue is an invalid state, wherein a data amount of the first data packet is less than a capacity of the second buffer, and the state of the first cache queue is set to the invalid state when a current data amount of the first buffer reaches a capacity of the first buffer;
and
when a data amount of the second buffer reaches the capacity of the second buffer, sending all data packets that are in the second buffer to a control plane device.

1 more element

A data packet processing apparatus, wherein the apparatus is included in a forwarding plane device, the forwarding plane device comprises a first buffer and a second buffer, the first buffer comprises at least one cache queue, and the apparatus comprises:

a processor, configured to:
when a first data packet is received, determine a first cache queue that is in the first buffer and that is used to store the first data packet;
a cache, configured to buffer the first data packet in the second buffer when a state of the first cache queue is an invalid state, wherein a data amount of the first data packet is less than a capacity of the second buffer, and the state of the first cache queue is set to the invalid state when a current data amount of the first buffer reaches a capacity of the first buffer;
and
a sending module, configured to:
when a data amount of the second buffer reaches the capacity of the second buffer, send all data packets that are in the second buffer to a control plane device.

3 more elements

Dependencies are inferred from the claim text.

Data packet processing method and apparatus, and device

Life of this patent

Data packet processing method and apparatus, and device

Life of this patent

Abstract

Claims14