Adaptive signal synchronization and glitch suppression for encryption engines

A decryption integrated circuit (IC) comprising:

• an interface configured to receive an encrypted block of data;
• and
• a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt the encrypted block of data to form a decrypted block of data wherein at least one computational stage included in the pipeline of the decryption data path includes:
• multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path;
• and
• a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at a downstream logic element of the at least one computational stage of the decryption data path at substantially a same time.

An apparatus for data decryption, the apparatus comprising:

• an interface configured to receive an encrypted block of data;
• and
• a decryption data path having a plurality of computational stages arranged in a pipeline configured to decrypt the encrypted block of data to form a decrypted block of data, wherein at least one of the computational stages included in the pipeline of the decryption data path includes:
• multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path;
• and
• a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at a downstream logic element of the at least one computational stage of the decryption data path at substantially a same time.

An artificial reality system comprising:

• an encryption data path having a plurality of computational stages arranged in a pipeline configured to encrypt a block of input data to form an encrypted block of data, wherein at least one of the computational stages included in the pipeline of the encryption data path includes:
• multiple asymmetric logical paths, wherein a first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path;
• and
• a glitch suppression register configured to synchronize the first signal with respect to the second signal such that the first signal and the second signal arrive at a downstream logic element of the at least one computational stage of the encryption data path at substantially a same time;
• and
• a head-mounted display (HMD) configured to output the encrypted block of data.