Error characteristic estimation for nand flash

A computer system comprising:

• a memory storing bits of a codeword;
• and
• an error correction code (ECC) decoder communicatively coupled with the memory and configured to:
• determine, based on voltage measurements, whether each bit stored in a portion of a block of the memory is a zero or a one;
• prior to decoding the codeword by performing a decoding procedure, estimate a first number of errors “E01” associated with bits each being a true zero and erroneously determined as a one and a second number of errors “E10” associated with bits each being a true one and erroneously determined as a zero;
• and
• perform the decoding of the codeword based on the decoding procedure after the first number of errors “E01” and the second number of errors “E10” are estimated.

A non-transitory computer-readable storage medium storing instructions that, upon execution on a computer system that includes a memory storing bits of a codeword and an error correction code (ECC) decoder decoding the codeword, cause the computer system to perform operations comprising:

• determining, based on voltage measurements, whether each bit stored in a portion of a block of the memory is a zero or a one;
• prior to decoding the codeword by performing a decoding procedure by the ECC decoder, estimating a first number of errors “E01” associated with bits each being a true zero and erroneously determined as a one and a second number of errors “E10” associated with bits each being a true one and erroneously determined as a zero;
• and
• performing the decoding of the codeword based on the decoding procedure after the first number of errors “E01” and the second number of errors “E10” are estimated.