Self-trim of integrated circuit

A system, comprising:

• a printed circuit board (PCB);
• a voltage supply node on the PCB;
• a device coupled to the PCB and to the voltage supply node, the device including:
• an electrical circuit having a bias terminal configured to receive a bias current from a current generator;
• a comparator having a first input, a second input, and a comparator output, the first input coupled to a bandgap reference source and the second input coupled to receive a voltage indicative of the bias current;
• a successive approximation register (SAR) circuit having an input coupled to the comparator output, the SAR circuit configured to provide at a SAR output a final trim code based on an output signal from the comparator;
• a memory coupled to the SAR output, the memory configured to store the final trim code;
• a digital-to-analog circuit (DAC) having an input coupled to the SAR output, and having an output;
• and
• a bias generator circuit having an input coupled to the output of the DAC and an output coupled to the electrical circuit, and configured to provide a control signal at an output of the bias generator to control the bias current.

A method, comprising:

• initializing a multi-bit trim code;
• and
• iteratively determining a final trim code, each iteration including:
• changing a bit of the multi-bit trim code from a first logic state to a second logic state;
• adjusting a bias current to produce an adjusted bias current;
• and
• responsive to the adjusted bias current changing by more than a threshold amount, changing the bit back to the first logic state.