Clock and data recovery devices with fractional-n pll

A clock data recovery (CDR) device comprising:

• a first phase detection module configured to receive digital input signal and determine a difference between the digital input signal and an output clock signal, the first phase detection module being configured to output triangular signals based on square signals, a gain scaling factor being determined using the triangular signals and the square signals;
• a loop filter module coupled to the first phase detection module and configured to generate a frequency control word;
• and
• a fractional-N phase lock loop (Frac-N PLL) configured to generate the output clock signal based on the frequency control word, the Frac-N PLL comprising a high-pass filter for processing the frequency control word, the high-pass filter comprising an inverse filter and an anti-aliasing filter.

A clock data recovery (CDR) device comprising:

• a first phase detection module configured to receive digital input signal and determine a difference between the digital input signal and an output clock signal;
• a loop filter module coupled to the first phase detection module and configured to generate a frequency control word;
• and
• a fractional-N phase lock loop (Frac-N PLL) configured to generate the output clock signal based on the frequency control word, the Frac-N PLL comprising a voltage controlled oscillator configured on a feedforward signal path and a current mode digital-to-analog converter;
• wherein the feedforward signal path comprises a square input signal and an output triangular signal, a digital gain scaling factor being determined using the square input signal and the output triangular signal.